Alif Semiconductor /AE512F80F5582AS_CM55_HE_View /OSPI0 /OSPI_IMR

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Interpret as OSPI_IMR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)TXEIM 0 (Val_0x0)TXOIM 0 (Val_0x0)RXUIM 0 (Val_0x0)RXOIM 0 (Val_0x0)RXFIM 0 (Val_0x0)TXUIM

TXUIM=Val_0x0, RXFIM=Val_0x0, RXOIM=Val_0x0, TXEIM=Val_0x0, RXUIM=Val_0x0, TXOIM=Val_0x0

Description

OSPI Interrupt Mask Register

Fields

TXEIM

Transmit FIFO Empty Interrupt Mask

0 (Val_0x0): Transmit FIFO Empty interrupt is masked.

1 (Val_0x1): Transmit FIFO Empty interrupt is not masked.

TXOIM

Transmit FIFO Overflow Interrupt Mask

0 (Val_0x0): Transmit FIFO Overflow interrupt is masked.

1 (Val_0x1): Transmit FIFO Overflow interrupt is not masked.

RXUIM

Receive FIFO Underflow Interrupt Mask

0 (Val_0x0): Receive FIFO Underflow interrupt is masked.

1 (Val_0x1): Receive FIFO Underflow interrupt is not masked.

RXOIM

Receive FIFO Overflow Interrupt Mask

0 (Val_0x0): Receive FIFO Overflow interrupt is masked.

1 (Val_0x1): Receive FIFO Overflow interrupt is not masked.

RXFIM

Receive FIFO Full Interrupt Mask

0 (Val_0x0): Receive FIFO Full interrupt is masked.

1 (Val_0x1): Receive FIFO Full interrupt is not masked.

TXUIM

Transmit FIFO Underflow Interrupt Mask

0 (Val_0x0): Transmit FIFO Underflow interrupt is masked

1 (Val_0x1): Transmit FIFO Underflow interrupt is not masked

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